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CR
Condition Register
PPC440x5 CPU Core User’s Manual Preliminary
Page 464 of 589
regsumm440core.fm.
September 12, 2002
CR
User Read/Write
See Condition Register (CR) on page 67.
Figure 10-3. Condition Register (CR)
0:3 CR0 Condition Register Field 0
4:7 CR1 Condition Register Field 1
8:11 CR2 Condition Register Field 2
12:15 CR3 Condition Register Field 3
16:19 CR4 Condition Register Field 4
20:23 CR5 Condition Register Field 5
24:27 CR6 Condition Register Field 6
28:31 CR7 Condition Register Field 7
0 3 4 7 8 1112 1516 1920 2324 2728 31
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
- PPC440x5 CPU Core 1
- User’s Manual 1
- Preliminary 1
- Copyright and Disclaimer 2
- Contents 3
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- PPC440x5 CPU Core Preliminary 10
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- About This Book 23
- Notation 24
- Related Publications 25
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- 1. Overview 27
- – 64-bit time base 28
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- 1.3 PPC440x5 Organization 30
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- 1.4 Core Interfaces 35
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- 2. Programming Model 39
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- 2.2 Registers 47
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- 2.3 Instruction Classes 53
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- .]” syntax 59
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- .]” and “[o]” 63
- 2.5 Branch Processing 64
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- 2.6 Integer Processing 71
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- 2.7 Processor Control 74
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- 2.8 User and Supervisor Modes 80
- 2.9 Speculative Accesses 81
- 2.10 Synchronization 82
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- 3. Initialization 85
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- 3.2 Reset Types 89
- 3.3 Reset Sources 89
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- Preliminary PPC440x5 CPU Core 101
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- TRANSIENT LINES 102
- LOCKED LINES 102
- NORMAL LINES 102
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- Programming Note: 105
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- 0 Cache line is not valid 113
- 1 Cache line is valid 113
- 0 TID enable 114
- 1 TID disable 114
- 4.3 Data Cache Controller 115
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- 5. Memory Management 133
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- 5.3 Page Identification 138
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- 5.4 Address Translation 140
- MSR[IS] for instruction fetch 141
- 5.5 Access Control 142
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- 5.6 Storage Attributes 145
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- 5.7 Storage Control Registers 147
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- 5.8 Shadow TLB Arrays 151
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- 5.11 TLB Parity Operations 155
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- 6. Interrupts and Exceptions 159
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- 6.3 Interrupt Processing 162
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- 6.5 Interrupt Definitions 175
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- Machine State Register (MSR) 198
- ME Unchanged 198
- All other MSR bits set to 0 198
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- 6.7 Exception Priorities 202
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- 7.1 Time Base 209
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- 7.2 Decrementer (DEC) 211
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- 7.4 Watchdog Timer 213
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- 8. Debug Facilities 219
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- 8.3 Debug Events 221
- IAC Event Enable Field 222
- IAC Mode Field 222
- IAC User/Supervisor Field 223
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- DAC Event Enable Field 226
- DAC Mode Field 227
- DAC User/Supervisor Field 228
- DVC Byte Enable Field 228
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- DVC Mode Field 232
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- 8.4 Debug Reset 238
- 8.5 Debug Timer Freeze 238
- 8.6 Debug Registers 238
- 01 Core reset 239
- 01 Reserved 240
- ≤ address < IAC2 241
- ≤ address < IAC4 241
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- 9. Instruction Set 249
- 9.2 Instruction Formats 250
- 9.3 Pseudocode 251
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- 9.4 Register Usage 253
- PPC440x5 core 254
- Registers Altered 255
- Add Carrying 256
- Add Extended 257
- Add Immediate 258
- Programming Note 258
- Add Immediate Carrying 259
- Invalid Instruction Forms 262
- AND with Complement 265
- AND Immediate 266
- AND Immediate Shifted 267
- Branch Conditional 270
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- ← CIA + 4 272
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- Programming Notes 284
- Count Leading Zeros Word 286
- Data Cache Block Allocate 295
- Data Cache Block Flush 296
- Exceptions 296
- Data Cache Block Store 298
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- Data Cache Block Set to Zero 303
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- Architecture Note 304
- Data Cache Read 305
- Divide Word 307
- Divide Word Unsigned 308
- Equivalent 310
- Extend Sign Byte 311
- Extend Sign Halfword 312
- Instruction Cache Block Touch 315
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- Instruction Cache Read 317
- Instruction Synchronize 320
- Load Byte and Zero 321
- Load Byte and Zero Indexed 324
- Load Halfword Algebraic 325
- Load Halfword and Zero 330
- Load Multiple Word 334
- Load Word and Reserve Indexed 339
- Load Word and Zero 341
- Load Word and Zero Indexed 344
- Move Condition Register Field 358
- Move From Condition Register 360
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- OR with Complement 393
- OR Immediate 394
- OR Immediate Shifted 395
- Return From Interrupt 397
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- Shift Left Word 405
- Shift Right Word 408
- Store Byte 409
- Store Byte with Update 410
- Store Byte Indexed 412
- Store Halfword 413
- Store Halfword with Update 415
- Store Halfword Indexed 417
- Store Multiple Word 418
- Store Word 422
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- Store Word with Update 426
- Store Word Indexed 428
- Subtract From 429
- Subtract From Carrying 430
- Subtract From Extended 431
- TLB Read Entry 435
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- TLB Synchronize 438
- Trap Word 441
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- Trap Word Immediate 444
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- Extended mnemonic for 445
- Invalid Instruction Forms: 446
- XOR Immediate 449
- XOR Immediate Shifted 450
- 10. Register Summary 451
- ICDBDR, ICDBTRH, ICDBTRL 452
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- 10.2 Reserved Fields 457
- 10.3 Device Control Registers 457
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- 0.Register Summary 459
- SPR 0x3B3 Supervisor R/W 460
- CCR0 (cont.) 461
- SPR 0x378 Supervisor R/W 462
- CCR1 (cont.) 463
- User Read/Write 464
- SPR 0x03A Supervisor R/W 465
- SPR 0x03B Supervisor R/W 466
- SPR 0x009 User R/W 467
- DAC1–DAC2 468
- SPR 0x134 Supervisor R/W 469
- DBCR0 (cont.) 470
- DBCR1 (cont.) 472
- Debug Control Register 2 473
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- DBCR2 (cont.) 474
- SPR 0x3F3 Supervisor R/W 475
- DBSR (cont.) 477
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- SPR 0x03D Supervisor R/W 480
- SPR 0x016 Supervisor R/W 481
- Decrementer Auto-Reload 482
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- DNV0–DNV3 483
- DTV0–DTV3 484
- DVC1–DVC2 485
- SPR 0x398 Supervisor R/W 486
- SPR 0x03E Supervisor R/W 487
- ESR (cont.) 488
- GPR0–GPR31 489
- IAC1–IAC4 490
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- INV0–INV3 494
- ITV0–ITV3 495
- SPR 0x399 Supervisor R/W 496
- IVOR0–IVOR15 497
- SPR 0x03F Supervisor R/W 498
- SPR 0x008 User R/W 499
- Machine Check Status Register 500
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- SPR 0x23A Supervisor R/W 501
- SPR 0x23B Supervisor R/W 502
- SPR 0x3B2 Supervisor R/W 503
- Supervisor R/W 504
- MSR (cont.) 505
- SPR 0x030 Supervisor R/W 506
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- Processor Version Register 508
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- SPR 39B Supervisor Read-Only 509
- SPRG0–SPRG7 510
- SPR 0x01A Supervisor R/W 511
- SPR 0x01B Supervisor R/W 512
- See Time Base on page 209 513
- Timer Control Register 515
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- Timer Status Register 516
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- SPR 0x100 (User R/W) 517
- Integer Exception Register 518
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- A.1 Instruction Formats 519
- A.1.1 Instruction Fields 520
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- A.1.2.5 X-Form 523
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- ←¬((RS) ⊕ (RB)) 538
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- ← (DCR(DCRN)) 543
- ← (MSR) 543
- ← (SPR(SPRN)) 544
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- September 12, 2002 571
- H, I, J, K 578
- Page 588 of 583 588
- Revision Log 589
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