IBM PPC440X5 Bedienungsanleitung PDF herunterladen (Seite 436)

100

101

tlbre

TLB Read Entry

PPC440x5 CPU Core User’s Manual Preliminary

Page 436 of 589

instrset.fm.

September 12, 2002

Registers Altered

•RT

• MMUCR[STID] (if WS = 0)

Invalid Instruction Forms

• Reserved ﬁelds

• Invalid WS value

Programming Notes

Execution of this instruction is privileged.

The PPC440x5 core does not automatically synchronize the context of the MMUCR[STID] field between a

tlbre instruction which updates the field, and a tlbsx[.] instruction which uses it as a source operand. There-

fore, software must execute an isync instruction between the execution of a tlbre instruction and a subse-

quent tlbsx[.] instruction to ensure that the tlbsx[.] instruction will use the new value of MMUCR[STID]. On

the other hand, the PPC440x5 core does automatically synchronize the context of MMUCR[STID] between

tlbre and tlbwe, as well as between tlbre and mfspr which specifies the MMUCR as the source SPR, so no

isync is required in these cases.

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